According to the prior art method for manufacturing multilayer wiring boards, generally, multiple double-sided copper-clad laminates having circuits formed thereto are alternately superposed with insulating adhesives to form an integrated multilayer structure, and through holes are provided at areas required for connection, having the inner walls of which plated. Higher wiring density is realized by minimizing the hole diameters and narrowing the wiring patterns, but since holes are formed even at unnecessary portions, wiring design must be performed to avoid the through holes, which becomes an obstacle for realizing higher density.
In order to solve the above-mentioned prior art problem, interlayer connection had been proposed to disuse through holes and to connect only the adjacent layers via non-through holes. One example thereof is a so-called build-up method including forming build-up layers on insulating boards having circuits formed thereto, forming non-through holes with laser or the like, plating the inner walls thereof and realizing connection, wherein the necessary number of layers are built up sequentially. Techniques for interlayer connection other than the build-up method that utilize conductive paste and anisotropic conductive material have been proposed by manufacturers and are offered in the market.
For example, patent document 1 discloses a method of forming holes in nonwoven fabric, filling conductive paste therein, and laminating and adhering copper foils or circuit boards on both sides thereof, and patent document 2 discloses a method of forming bumps on a copper foil using conductive material, superposing a synthetic resin sheet, and laminating and adhering the copper foil with circuit boards. Further, patent document 3 discloses a method for realizing interlayer connection using solder, sequentially forming metal projections and solders on wiring terminal portions of circuit patterns, arranging the circuit patterns so that the solders are opposed, and melting the solders to realize electrical connection. Moreover, patent document 4 discloses a double-sided printed board in which conductive resin composition with a specific composition is filled in via holes formed on an insulating substrate, and the conductive resin composition is hardened in the via holes so that the upper and lower electrode layers on the surfaces of the insulating substrate are electrically connected.    Patent document 1: Japanese Patent Application Laid-Open Publication No. 10-200258    Patent document 2: Japanese Patent Application Laid-Open Publication No. 10-79579    Patent document 3: Japanese Patent Application Laid-Open Publication No. 5-90763    Patent document 4: Japanese Patent No. 3038210